In recent years, integrated circuit design has been trending towards increasingly difficult demands on lowering power consumption and cost along with enhancing performance. In the design of front-end analog circuits, an efficient analog-to-digital converter (ADC) can drastically enhance the overall system performance. The ADC is responsible for converting the received analog signals into digital signals, and providing the digital signals for the operation of the back-end digital signal processing unit. Therefore, characteristics of the ADC such as its dynamic range, resolution, accuracy, linearity, sampling speed, power consumption, and its input stage are crucial factors which influence the overall system performance, and these characteristics serve as several parameters for evaluating the performance of the ADC.
For two categories in resolution and sampling speed, the application range of an ADC with 8-14 bits and one to several hundred mega samples per second (MSPS) is quite broad. Applications such as in the front-end of the base frequency or the intermediate frequency of a communication system, a biomedical imaging process such as the front-end of a ultrasonic imaging system, and the front-end of a laser array system are all within the range of applications. The ADC has many types of configurations, and when manufacturing an ADC matching the aforementioned specifications, a diverse array of configurations can be chosen. The mainstream ADC applied commercially is the pipeline analog-to-digital converter, or the pipeline ADC. However, in recent years, articles in prominent international journals have gravitated towards the successive approximation register analog-to-digital converter (SAR ADC) as a popular research direction, because the SAR ADC configuration almost does not require a direct current bias voltage. Since the SAR ADC requires a good amount of digital circuits for control and signal processing, when the manufacturing process enters the deep sub-micron, the chip area and the power consumption needed for a portion of the digital circuits can be effectively reduced. Accordingly, the SAR ADC is suitable for developing the intellectual property from a large scale system-on-chip (SoC). In many disclosures, the SAR ADC has lower consumption and smaller chip area when compared to the pipeline ADC with the same specification requirements. Therefore, the technical development of the SAR ADC framework has become an active field of research.
In the SCA SAR ADC, a key of linearity lies in matching of the composed capacitors in the DAC. Due to an influence of process variation, a designer generally uses a larger unit capacitance to satisfy the demand of matching, such that the DAC is accounted for a large proportion in chip area and power consumption in the whole SAR ADC, and the larger area of the DAC represents that a driving circuit of the DAC is required to have a greater driving force, which further increase the area and the power consumption. Since the cost of the digital circuit is quite low, if the processing technique of the digital circuit can be used to decrease or even eliminate the demand of the DAC on matching of the composed elements therein, the whole chip area and power consumption of the SCA SAR ADC can be effectively decreased.